Multi-layered structure including an epitaxial layer having a low dislocation defect density, semiconductor device comprising the same, and method of fabricating the semiconductor device

ABSTRACT

A multi-layered structure of a semiconductor device includes a substrate, and a heteroepitaxial layer having a low dislocation defect density on the substrate. The heteroepitaxial layer consists of a main epitaxial layer and at least one intermediate epitaxial layer sandwished in the main epitaxial layer. At their interface, the heteroepitaxial layer, i.e., the bottom portion of the main epitaxial layer, and the substrate have different lattice constants. Also, the intermediate epitaxial layer has a different lattice constant from that of the portions of the main epitaxial layer contiguous to the intermediate epitaxial layer. The intermediate epitaxial layer also has a thickness smaller than the net thickness of the main epitaxial layer such that the intermediate epitaxial layer absorbs the strain in the heteroepitaxial layer. Thus, it is possible to obtain a multi-layered structure comprising an epitaxial layer that is relatively thin and has a low dislocation defect density.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a semiconductor device comprising anepitaxial layer. More particularly, the present invention relates to amulti-layered structure including an epitaxial layer, to a semiconductordevice comprising the same, and to a method of fabricating thesemiconductor device.

2. Description of the Related Art

Recently, the use tensile-strained silicon as a channel layer has beenresearched as a way to improve carrier mobility in a field effecttransistor (hereinafter, referred to as a FET).

In general, the tensile-strained silicon channel layer is produced byforming an Si_(1-x)Ge_(x) virtual substrate on a silicon substrate,annealing the resultant structure to relax the structure, and forming asilicon channel layer on the relaxed Si_(1-x)Ge_(x) virtual substrate.As a result, the tensile-strained silicon channel layer can be obtainedby using the tensile strain in silicon caused by a lattice mismatchbetween the relaxed Si_(1-x)Ge_(x) virtual substrate and the siliconchannel layer.

In forming the Si_(1-x)Ge_(x) virtual substrate on the siliconsubstrate, dislocations thread within the Si_(1-x)Ge_(x) virtualsubstrate when the strain caused by the lattice mismatch with thesilicon substrate is relaxed. The threads of the dislocations in thevirtual substrate accumulate at the top portion of the virtualsubstrate, and propagate into the silicon channel, thereby causingcarrier scattering to occur in the channel. Carrier scattering preventsthe FET from providing high carrier mobility.

An attempt to reduce the dislocation defect density of the epitaxiallayer is described in U.S. Pat. No. 5,659,187. The patent discloses thatan epitaxial layer, used as a virtual substrate, and having acomposition graded by 0.025 to 2% per 1,000 Å in its direction ofthickness, has a reduced dislocation defect density.

Meanwhile, in order to form a tensile-strained silicon channel layerthat provides sufficient carrier mobility at the top of anSi_(1-x)Ge_(x) virtual substrate, the value of X at the top surface ofthe Si_(1-x)Ge_(x) virtual substrate must be 0.2 or more. Andpreferably, the value of X at the bottom surface of the Si_(1-x)Ge_(x)virtual substrate contiguous to (i.e., interfacing with) the siliconsubstrate is 0.

Therefore, in a case in which an Si_(1-x)Ge_(x) layer is used as thevirtual substrate, and the composition of the Si_(1-x)Ge_(x) was gradedby 2% per 1,000 Å as described in the above-mentioned patent, theSi_(1-x)Ge_(x) virtual substrate would have to be at least 1 μm thick ifthe value of X were to be 0 at the bottom surface and 0.2 or more at thetop surface. Such a thick epitaxial layer presents problems inimplementing a subsequent photolithography process.

Another attempt to reduce the dislocation defect density, proposes achemical mechanical polishing (CMP) process to eliminate the threads ofthe dislocations accumulating at the top portion of the epitaxial layer.

Nonetheless, despite the use of the above-described methods, thedislocation defect density of an Si_(1-x)Ge_(x) virtual substrateremains high—on the order of 10⁶/cm².

SUMMARY OF THE INVENTION

An object of the present invention is to solve the above-describedproblems and limitations of the prior art.

Thus, it is one object of the present invention to provide amulti-layered structure comprising an epitaxial layer that is relativelythin and yet has a low dislocation defect density.

It is thus another object of the present invention to provide asemiconductor device having a multi-layered structure comprising anepitaxial layer and having high carrier mobility.

According to one aspect of the present invention, the invention providesa multi-layered structure comprising a substrate, and a heteroepitaxiallayer disposed on the substrate. The heteroepitaxial layer consists of amain epitaxial layer having a lattice constant different from that ofthe substrate, and at least one intermediate epitaxial layer sandwichedwithin the main epitaxial layer. The intermediate epitaxial layer has alattice constant different from portions of the main epitaxial layercontiguous to the intermediate epitaxial layer. Also, the intermediateepitaxial layer has a thickness smaller than that of the main epitaxiallayer such that the intermediate epitaxial layer absorbs the strain inthe heteroepitaxial layer.

The main epitaxial layer may have a graded composition from its bottomsurface to its top surface or the main epitaxial layer may have auniform composition throughout its entirety.

Preferably, the main epitaxial layer is composed of Si_(1-x)Ge_(x)(0<X<1). In this case, the substrate is composed of monocrystallinesilicon, and the value of X may be 0 at the bottom surface of the mainepitaxial layer. The value of X may also thus increase in a graduatedmanner to the top surface of the main epitaxial layer or the value of Xmay be constant throughout the main epitaxial layer.

The intermediate epitaxial layer may have a uniform compositionthroughout. The intermediate epitaxial layer may be formed of Si, SiC,or SiGeC. Preferably, the sum of the thicknesses of the at least oneintermediate epitaxial layer is ½ or less of the net thickness of themain epitaxial layer.

According to another aspect of the present invention, the inventionprovides a semiconductor device comprising a strained channel layer, andwherein the heteroepitaxial layer is interposed between the substrateand the channel layer. The channel layer may be a tensile-strainedlayer. Also, the channel layer may be composed of Si or SiC.

As was mentioned above, the composition of the main epitaxial layer maybe graded from the bottom surface to the top surface of the layer. Inthis case, the semiconductor device preferably further comprises auniform epitaxial layer interposed between the heteroepitaxial layer andthe channel layer. The composition of the uniform epitaxial layer is thesame as that at the top surface of the heteroepitaxial layer.

According to still another aspect of the present invention, theinvention provides a method of fabricating the semiconductor deviceincluding steps of providing a substrate, forming the heteroepitaxiallayer on the substrate whereby the intermediate epitaxial layer willabsorb the strain in the heteroepitaxial layer, annealing theheteroepitaxial layer, and forming the channel layer on the annealedheteroepitaxial layer.

The substrate on which the heteroepitaxial layer is formed may bepolished using a chemical mechanical polishing (CMP) process, before thechannel layer is formed.

Also, the heteroepitaxial layer may be formed by ultrahigh vacuumchemical vapor deposition (UHVCVD), reduced pressure chemical vapordeposition (RPCVD), low pressure chemical vapor deposition (LPCVD), ormolecular beam epitaxy (MBE).

Also, in the case mentioned above in which the heteroepitaxial layer hasa graded composition, a uniform epitaxial layer may be formed on theheteroepitaxial layer before the channel layer is formed, wherein thecomposition of the uniform epitaxial layer is the same as that of thetop portion of the heteroepitaxial layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the presentinvention will be more clearly understood from the following detaileddescription taken in conjunction with the accompanying drawings, inwhich:

FIGS. 1A and 1B are sectional views of a substrate, illustrating amethod of fabricating a semiconductor device according to the presentinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The preferred embodiments of the present invention will be described indetail hereinafter with reference to FIGS. 1A and 1B.

Referring first to FIG. 1A, a heteroepitaxial layer is formed on asubstrate 100. The substrate 100 may be made of monocrystalline silicon.The heteroepitaxial layer comprises a main epitaxial layer 200 and atleast one intermediate epitaxial layer 300 sandwiched within the mainepitaxial layer 200. The heteroepitaxial layer having the intermediateepitaxial layer 300 may be formed by ultrahigh vacuum chemical vapordeposition (UHVCVD), reduced pressure chemical vapor deposition (RPCVD),low pressure chemical vapor deposition (LPCVD), or molecular beamepitaxy (MBE). Subsequently, the heteroepitaxial layer comprising the atleast one intermediate epitaxial layer 300 is annealed. Preferably, theannealing process is performed for at least one hour at 950° C.

The main epitaxial layer 200 is formed of a material having a latticeconstant different from that of the substrate 100. Generally, anepitaxial layer is strained by a lattice mismatch with an underlyingsubstrate, and dislocations occur in the epitaxial layer when the strainis relaxed by the annealing process. However, according to the presentinvention, dislocations can be prevented from occurring in the mainepitaxial layer 200 by forming the intermediate epitaxial layer 300therein. Here, the intermediate epitaxial layer 300 must have a latticeconstant different from that of the portions of the main epitaxial layer200 contiguous to the intermediate epitaxial layer 300.

Assuming that the thicknesses of the main epitaxial layer 200 and theintermediate epitaxial layer 300 are small, the magnitudes of the strainin the main epitaxial layer 200 and the intermediate epitaxial layer 300are identical. In addition, the orientation of the strain in the mainepitaxial layer 200 is different from that in the intermediate epitaxiallayer 300 because the lattice constants of the main epitaxial layer 200and the intermediate epitaxial layer 300 are mismatched. That is, themain epitaxial layer 200 and intermediate epitaxial layer 300 arestrained in tension and compression, or in compression and tension,respectively, and the levels of the strain are identical. This conditioncan be represented by the following mathematical expression:Be₁ ²h₁=Be₂ ²h₂wherein B=2G(1+n)/(1−n), G=shear modulus, n=Poisson's ratio, e=latticemismatch, and h=layer thickness.

Referring to the mathematical expression, the larger the net thickness(h₂) of the main epitaxial layer 200 becomes, the greater is the strainapplied to the intermediate epitaxial layer 300. Accordingly, when thethickness of the main epitaxial layer 200 is sufficiently large relativeto the thickness of the intermediate epitaxial layer 300, theintermediate epitaxial layer 300 absorbs almost all of the strain in theheteroepitaxial layer. Accordingly, the thickness of the intermediateepitaxial layer 300 must be small compared to the net thickness of themain epitaxial layer 200. Preferably, the thickness of the intermediateepitaxial layer 300 is ½ of that of the main epitaxial layer 200. And,it follows that when more than one intermediate epitaxial layer 300 ispresent in the heteroepitaxial layer, the sum of the thicknesses of theintermediate epitaxial layers 300 is preferably ½ of the net thicknessof the main epitaxial layer 200.

The annealing process relaxes the strain at the interface between theintermediate epitaxial layer 300 and the main epitaxial layer 200. Therelieving of strain due to the annealing process causes dislocations tooccur in the intermediate epitaxial layer 300 that has absorbed almostall of the strain from the main epitaxial layer 200. However, thedislocations are suppressed in the main epitaxial layer 200 in which thestrain has been relieved by the intermediate epitaxial layer 300.Accordingly, the main epitaxial layer 200 has a low number ofdislocations, i.e., a low dislocation defect density.

The main epitaxial layer 200 may have a graded composition from thebottom surface 200 a, contiguous to the substrate 100, to the topsurface 200 b thereof, which is to say from the bottom surface to thetop surface of the heteroepitaxial layer. Alternatively, the mainepitaxial layer 200 may have a uniform composition from the bottomsurface 200 a to the top surface 200 b.

The main epitaxial layer 200 may be formed of Si_(1-x)Ge_(x) (0<X<1).

In the case in which the substrate 100 is a monocrystalline siliconsubstrate and the main epitaxial layer 200 has a graded composition, itis possible for the value of X to be 0 at the bottom surface 200 a ofthe heteroepitaxial layer. Preferably, the value of X is 0.2 or more atthe top surface 200 b. Generally, the dislocation density of the gradedmain epitaxial layer 200 can be minimized solely by fabricating the mainepitaxial layer 200 such that the value of X varies by 0.02 or less per1,000 Å in the direction of thickness of the heteroepitaxial layer.However, as described above, according to the present invention,dislocations in the main epitaxial layer 200 can be suppressed byforming the intermediate epitaxial layer 300 in the main epitaxial layer200. Accordingly, the value of X in a main epitaxial layer formed ofSi_(1-x)Ge_(x) can vary by 0.02 or more per 1,000 Å in the direction ofthickness of the heteroepitaxial layer. Consequently, when the value ofX is 0.2 at the top surface 200 b of the heteroepitaxial layer, thethickness of the main epitaxial layer 200 can be 1 μm or less and stillhave a low dislocation defect density.

Alternatively, the value of X in the composition Si_(1-x)Ge_(x) of themain epitaxial layer 200 may be constant from the bottom surface 200 aof the main epitaxial layer to the top surface 200 b. In this case, thevalue of X may be 0.2 or more. In general, in the case of an epitaxiallayer having a uniform composition, the layer is formed thick enough tolimit the ability of dislocations to propagate all the way to the topsurface of the epitaxial layer. However, according to the presentinvention as described above, the heteroepitaxial layer can berelatively thin without incurring dislocations because of the forming ofthe intermediate epitaxial layer 300 prior to the annealing process.Such a relatively thin (hetero)epitaxial layer facilitates a subsequentphotolithography process.

The intermediate epitaxial layer 300 may have a uniform composition.Preferably, the intermediate epitaxial layer 300 is formed of Si, SiC,or SiGeC.

Referring to FIG. 1B, preferably, the substrate 100 on which theheteroepitaxial layer is formed is polished using a chemical mechanicalpolishing (hereinafter, referred to as CMP) process. As described above,although it is unlikely that a significant number of dislocation defectswill be present at the top surface 200 b of the heteroepitaxial layer,the CMP process will nonetheless eliminate any dislocation defects thathave been incurred at the top surface 200 b.

Subsequently, a uniform epitaxial layer 400 (an epitaxial layer having auniform composition) may be formed on the polished heteroepitaxiallayer. The uniform epitaxial layer 400 may be omitted in the case inwhich the main epitaxial layer 200 has a uniform composition. Theuniform epitaxial layer 400 has the same composition as that of theheteroepitaxial layer at the top surface 200 b, i.e., at the surface atwhich the uniform epitaxial layer 400 interfaces with theheteroepitaxial layer.

A channel layer is formed on the uniform epitaxial layer 400. Thechannel layer is formed of a material having a lattice constantdifferent from that of the uniform epitaxial layer 400, i.e. differentfrom that at the top surface 200 b of the heteroepitaxial layer.Alternatively, the channel layer is formed directly on theheteroepitaxial layer in the above-described case in which the uniformepitaxial layer 400 is omitted. In this latter case, the channel layeris formed of a material having a lattice constant different from that ofthe heteroepitaxial layer. For example, the channel layer may be formedof Si or SiC.

As a result, the channel layer is formed as a strained channel layer 500due to a lattice mismatch with the uniform epitaxial layer 400 or theheteroepitaxial layer. When the lattice constant of the channel layer issmaller than that of the uniform epitaxial layer 400 or theheteroepitaxial layer, the strained channel layer 500 is strained intension, i.e., is a tensile-strained channel layer 500. In the case inwhich the channel layer 500 is formed of Si and the uniform epitaxiallayer 400 or the heteroepitaxial layer 200 is formed of Si_(1-x)Ge_(x)(0<X<1), the value of X is preferably 0.2 or more. This is becauseproper carrier mobility is obtained in the channel layer 500 when X hasa value of 0.2 or more in this case.

Meanwhile, few dislocation defects propagate into the channel layer 500because of the low dislocation defect density of the main epitaxiallayer 200 and the lack of dislocation defects incurred at the topsurface 200 b of the heteroepitaxial layer 200. Accordingly, carrierscattering is reduced and therefore, carrier mobility in the channellayer is high.

According to the present invention as described above, a thin epitaxiallayer having a low dislocation defect density can be provided by formingthe epitaxial layer as heteroepitaxial layer consisting of a mainepitaxial layer and an intermediate epitaxial layer having a thicknessless than that of the main epitaxial layer. Also, the present inventionprovides a semiconductor device having high carrier mobility.

Although the present invention have been described above in detail withrespect to the preferred embodiments thereof, those skilled in the artwill appreciate that various modifications and/or additions can be madeto the preferred embodiments without departing from the true scope andspirit of the invention as defined by the appended claims.

1-24. (canceled)
 25. A method of fabricating a semiconductor device,comprising: providing a substrate; forming a heteroepitaxial layer onthe substrate by forming a main epitaxial layer having a bottom surfaceon said substrate, and a top surface, the lattice constant of the mainepitaxial layer being different from that of the substrate, and formingat least one intermediate epitaxial layer that is situtated within themain epitaxial layer above said bottom surface and beneath said topsurface, the intermediate epitaxial layer having a lattice constantdifferent from that of portions of the main epitaxial layer interfacingwith the intermediate epitaxial layer, and the thickness of theintermediate epitaxial layer being smaller than the net thickness of themain epitaxial layer; annealing said heteroepitaxial layer, whereby theintermediate epitaxial layer absorbs the strain imposed on theheteroepitaxial layer by said annealing; and forming on the annealedheteroepitaxial layer a channel layer having a lattice constantdifferent from that of said heteroepitaxial layer at the top surface ofsaid main epitaxial layer.
 26. The method according to claim 25, andfurther comprising polishing the substrate on which the heteroepitaxiallayer is formed using a chemical mechanical polishing (CMP) processbefore forming the channel layer.
 27. The method according to claim 25,wherein the heteroepitaxial layer is formed by ultrahigh vacuum chemicalvapor deposition (UHVCVD), reduced pressure chemical vapor deposition(RPCVD), a low pressure chemical vapor deposition (LPCVD), or molecularbeam epitaxy (MBE).
 28. The method according to claim 25, wherein saidforming of the main epitaxial layer comprises varying the compositionthereof from its bottom surface to its top surface.
 29. The methodaccording to claim 28, and further comprising forming a uniformepitaxial layer having a uniform composition throughout on theheteroepitaxial layer before forming the channel layer, and wherein thecomposition of the uniform epitaxial layer is the same as that of themain epitaxial layer at the top surface thereof.
 30. The methodaccording to claim 25, wherein the main epitaxial layer is formed so asto have a uniform composition throughout.
 31. The method according toclaim 25, wherein said forming of the main epitaxial layer comprisesforming a layer of Si_(1-x)Ge_(x) (0<X<1) on the substrate.
 32. Themethod according to claim 31, wherein the substrate provided is amonocrystalline silicon substrate, and said main epitaxial layer isformed such that the value of X is 0 at the bottom surface of the mainepitaxial layer and varies in a graduated manner from the bottom surfaceto the top surface thereof.
 33. The method according to claim 32,wherein the main epitaxial layer is formed such that the value of X is0.2 or more at the top surface thereof.
 34. The method according toclaim 31, wherein the main epitaxial layer is formed such that the valueof X is constant throughout.
 35. The method according to claim 34,wherein the main epitaxial layer is formed such that the value of X is0.2 or more.
 36. The method according to claim 25, wherein theintermediate epitaxial layer is formed such that its composition isuniform throughout.
 37. The method according to claim 25, wherein saidforming of the intermediate epitaxial layer consists of forming a layerof Si, SiC, or SiGeC.
 38. The method according to claim 25, wherein theheteroepitaxial layer is formed such that the sum of the thicknesses ofthe at least one intermediate epitaxial layer is ½ or less of the netthickness of the main epitaxial layer.
 39. The method according to claim25, wherein the channel layer is formed of a material having a latticeconstant smaller than that of the heteroepitaxial layer at the topsurface of said main epitaxial layer.
 40. The method according to claim25, wherein said forming of a channel layer comprises forming thechannel layer of Si or SiC.